1. Field of the Invention
The present invention relates to a PLL frequency synthesizer including a voltage controlled oscillator and a phase control loop which controls the oscillation frequency of the voltage controlled oscillator, integrated on a semiconductor device, and a method of automatically selecting the oscillation frequency of a voltage controlled oscillator.
2. Description of the Related Art
In various wireless communication systems, frequencies in receiving signals and transmitting signals vary in accordance with the communication systems. A PLL frequency synthesizer including an oscillator and a phase locked loop (PLL) is capable of determining the frequency accepted in the communication system.
FIG. 13 shows an example of a conventional PLL frequency synthesizer.
The conventional circuit includes a voltage controlled oscillator (VCO) 100, a phase locked loop unit (PLL unit) 200 and a low pass filter (LPF) 300.
The PLL unit 200 includes a buffer 201, a reference frequency divider (REF divider) 202, a buffer 203, a SIG frequency divider (SIG divider) 204, a phase comparator 205, and a charge pump 206. A reference signal having a reference frequency fref is input to the REF divider 202 through the buffer 201. The REF divider 202 divides the input signal fref by R to output a signal fref/R. The signal fVCO output from the VCO 100 is input to the SIG divider 204 through the buffer 203. The SIG divider 204 divides the input signal fVCO by N to output a signal fVCO/N. The signal fref/R and the signal fVCO/N are input to the phase comparator 205. The phase comparator 205 compares the input signals fref/R and fVCO/N to output an output signal based on the frequency error of the signals fref/R and fVCO/N to the charge pump 206. The charge pump 206 outputs an output signal Iout based on the error. The output signal Iout is converted to a voltage value, which becomes the voltage Vtune, by the LPF 300.
The VCO 100 generally includes a voltage-controlled oscillator. When the control voltage Vtune is input to the VCO 100, the VCO 100 outputs a signal having the oscillation frequency fVCO, which is in turn input to the SIG divider 204 through the buffer 203, based on the input control voltage Vtune. Therefore, the VCO frequency fVCO is adjustable by controlling the control voltage Vtune.
Here, the PLL unit 200 generates the control current Iout such that the frequencies and the phases of the input signals, fVCO/N and fref/R input to the phase comparator 205 become same. Therefore, the following frequency relationship can be obtained in a steady state “fVCO=N×fref/R”.
The value of the dividing ratio N of the SIG-divider 204 is determined by a frequency dividing ratio setting signal externally input to the PLL unit 200. Therefore, an output signal having a desired frequency fVCO can be obtained by changing the frequency dividing ratio setting signal.
The VCO 100 and the PLL unit 200 shown in FIG. 13 are usually integrated on a semiconductor device. The semiconductor device includes a plurality of circuit elements such as transistors, resistors and condensers where those circuit elements are connected such that the semiconductor device realizes required circuit operations and functions.
Mainly, there are four requirements for the VCO 100 and the PLL unit 200, “high integration”, “low noise”, “high-speed responsibility” and “wider bandwidth”.
“High integration” means that all circuits constructing the VCO and the PLL can be integrated on a semiconductor device. “Low noise” means that the noise components in the output signal VCO from the VCO 100 output in accordance with the input signal controlled by the PLL unit 200 can be decreased. This is determined by the output power ratio CN indicating output power of the carrier component to that of the noise component. “High-speed responsibility” means that the response time required for the output frequency to be stabilized to a desired value after the reference frequency is input to the VCO 100. “Wider bandwidth” means that the bandwidth of the VCO frequency fVCO of the VCO 100 is increased.
FIG. 14 shows another example of a conventional PLL frequency synthesizer.
The conventional PLL frequency synthesizer shown in FIG. 14 includes an oscillator unit (VCO unit) 110, a VCO selector 120, a phase controller (PLL unit) 200A and a low pass filter unit (LPF unit) 300.
The VCO unit 110 includes an LC oscillator. The LC oscillator includes an inductor (L) 111, a variable capacitance Cv and a negative mutual conductance (−G) 113 connected in parallel with each other. The output frequency of the VCO is determined by the resonance frequency of the inductor (L) 111 and the capacitor Cv. The LC oscillator oscillates at the resonance frequency with the function of the negative mutual conductance (−G) 113. In the VCO unit 110, the value of the variable capacitance Cv which includes a varactor diode continuously changes in accordance with the input control-voltage Vcnt, this in turn changes the resonance frequency of the LC resonance circuit. Thus, the VCO frequency fVCO of the VCO changes and therefore, it is possible to continuously change the output frequency fVCO of the VCO unit by the control voltage Vcnt.
Furthermore, the VCO unit 110 further includes m fixed-value capacitors C0, C1, C2, . . . , and Cm-1 connected to the variable capacitor 112 in parallel through the switches S0, S1, S2, . . . , and Sm-1, respectively. By selecting the switches S0, S1, S2, . . . , and Sm-1, the resonance frequency of the LC oscillator can be discretely changed and then the output frequency of the VCO unit 110 can be discretely adjustable.
FIG. 15 shows the relationship between the control voltage and the output frequency (Vcnt−fVCO characteristics) of the VCO unit 110 shown in FIG. 14. It is shown that the output frequency fVCO changes discretely by selecting the fixed value capacitors C0, C1, C2, . . . , and Cm-1 and continuously by the variable capacitance (CV) 112. Thus, broadband oscillation of the fVCO of the VCO unit 110 is realized by a combination of the discrete frequency change depending on the fixed-value capacitors C0, C1, C2, . . . , and Cm-1 and the continuous frequency change depending on the variable capacitance Cv.
Referring back to FIG. 14, the VCO-selector unit 120 controls on/off of the switches S0, S1, S2, . . . , and Sm-1 of the fixed-value capacitors C0, C1, C2, . . . , and Cm-1 of the VCO unit 110, respectively. The input signals to the VCO-selector unit 120 are a signal fCLK obtained by dividing the VCO frequency fVCO by the prescaler (PSC) 221 of the N-divider 220 and a signal ENCLK obtained by dividing the reference signal by the R-divider 210.
The signal fCLK is an operating clock of the counter 121. The active period of the counter 121 is determined by the signal ENCLK. The counter 121 counts up the signal fCLK during a period provided by the signal ENCLK. The count M′ of the counter 121 is determined by the period provided by the signal ENCLK and the frequency fCLK. The count M′ is then transferred to the calculation circuit 122.
The calculation circuit 122 calculates the count difference M−M′, where M is the count corresponding to the required frequency and M′ is the count of the counter 121, and compares the count difference M−M′ with the predetermined convergence range ΔM.
In the case when M−M′<ΔM, the process for VCO selection is terminated. However, in the case when M−M′>ΔM, whether the VCO frequency fVCO is higher than the required frequency or lower is judged and the selection signal VCOSEL[m-1:0] is changed such that the VCO frequency fVCO approaches to the required frequency. With this, some of the control signals vcosel<0>, vcosel<1>, vcosel<2>, . . . , and vcosel<m-1> are generated though the decoder 123 to control the switches S0, S1, S2, . . . , and Sm-1 and determine the on/off of fixed-value capacitors C0, C1, C2, . . . , and Cm-1.
The PLL unit 200A includes a R-divider 210 which outputs the signal fr obtained by dividing the reference signal fref by R, a N-divider 220 which outputs the signal fn obtained by dividing the VCO frequency fVCO of the VCO unit 110 by N, a phase comparator 230 which compares the phase of the signal fr with the signal fn, and a charge pump 240 which generates the output current Iout based on the phase error obtained by the phase comparison of the phase comparator 230. The output current Iout of the charge pump 240 is converted to the control voltage Vcnt through the LPF 300.
The N-divider 220 includes a prescaler (PSC) 221 and a N/A-counter 222. The PSC 221 receives the VCO frequency fVCO from the VCO unit 110, divides the VCO frequency fVCO by the constant value P, and generates a P-divided signal fpsc. The N/A-counter divides the P-divided signal fpsc by the constant value N′, and generates a N-divided signal fn (=fVCO/PN′).
The operation of the PLL frequency synthesizer shown in FIG. 14 will be explained.
A. Discretely Adjusting Process for the VCO Frequency FVCO 
The discretely adjusting process can be obtained by controlling the VCO unit 110 by the VCO selector unit 120. The VCO selector unit 120 selects some of the fixed-value capacitors C0, C1, C2, . . . , and Cm-1 to be connected therewith with the control voltage Vcnt for the VCO unit 110 is kept at the constant voltage. At this time, the selection signal VCOSEL[m-1:0] is selected such that the VCO frequency fVCO approaches nearest to the required frequency. The phase comparator 230 and the charge pump 240 of the PLL unit 200A is not operated at this time. Further, the VCO frequency fVCO cannot be completely matched with the required frequency as the VCO frequency fVCO changes discretely.
B. Continuously Adjusting Process for the VCO Frequency fVCO 
The continuously adjusting process for the VCO frequency fVCO can be obtained by the selection signal CF[m-1:0] of the PLL unit 200A to the VCO unit 110. When the discretely adjusting process for the VCO frequency fVCO is completed, the selection signal VCOSEL[m-1:0] is fixed at the final result and the operation of the VCO selector unit 120 is terminated. Then, the control voltage Vcnt to the VCO unit 110 is released from the previous fixed voltage. Then, the operation of the phase comparator 230 and the charge pump 240 of the PLL unit 200A is started. Hence, the control voltage Vcnt is controlled by the PLL unit 200A, so that the VCO frequency fVCO changes continuously. Since the VCO frequency fVCO continuously changes in this process, the VCO frequency fVCO can be completely matched with the required frequency.
It is disclosed in Japanese Laid-open patent publication 2001-339301, that the frequency synthesizer is provided with a prescaler and a counter that outputs a frequency division signal of an output of the VCO, a reference frequency divider that frequency-divides the frequency of a reference signal source, a frequency adjustment means that detects a frequency error of an output signal between the counter and the reference frequency divider and provides the output of a signal to switch capacitance or resistance of a resonance circuit of the VCO depending on the result of detection, and a bias control means that applies an optical voltage V1 to a control voltage terminal of the VCO at the operation of the frequency adjustment means to bring the output signal of a charge pump to a high impedance state. It is described in the publication that since the resonance frequency of the resonance circuit is changed in response to the actual oscillated frequency of the VCO, the VCO is phase-locked at a desired frequency and since the VCO can be integrated as an IC, the VCO can be miniaturized at a low cost.
It is disclosed in Japanese Laid-open patent publication 2003-152535, that a VCO, constituting the PLL circuit, is configured to enable it to operate in a plurality of bands. In the state wherein the controlling voltage of the oscillation circuit of the VCO is fastened to a predetermined value, the oscillation frequencies of the oscillation circuit are measured in the respective bands to store them in a memory circuit. Then, by comparing the stored frequency measurement values with the set value for assigning the band given, when operating the PLL circuit, the band used actually in the oscillation circuit is determined from the comparison result thereof.
It is disclosed in Japanese Laid-open patent publication 2003-264461, that in a frequency synthesizer having a voltage-controlled oscillator capable of selecting a plurality of frequency bands by using a control signals CSW1 to 4, the control voltage Vt of the voltage-controlled oscillator is fixed to a constant voltage V2 when a power is applied, the control signals CSW1 to 4 are varied at fixed time intervals on the basis of a reference frequency, the oscillation frequencies of the respective frequency bands at Vt=V2 are detected by a counter and stored in a register. The values of the CSW1 to 4 are determined by converting the division ratio data into frequency data by using a conversion circuit and comparing the resultant frequency data with a value of the register when the division ratio data is inputted.
It is disclosed in Japanese Laid-open patent publication 2003-318732, that an oscillation circuit (VCO) comprising the PLL circuit is constructed operably in several bands. A control voltage (Vc) of the oscillation circuit is fixed to a predetermined value (V DC), and oscillation frequency of the oscillation circuit in each of the bands is measured and stored in a storage circuit. A set value for specifying the band, given during the operation of the PLL and the measured frequency value which is stored in this way, are compared and the band to be actually used in the oscillation circuit is determined by the result of comparison. Also, the frequency difference between the maximum frequency of the selected band and the set frequency is found, and a control voltage which is closest to the set frequency is determined from the frequency difference ad the variable range of frequency of the selected band. The control voltage is applied to the oscillation circuit for starting its oscillation operations, and then a PLL loop is closed and locked.
As for the conventional PLL frequency synthesizer shown in FIG. 14, the repetitive times of a step for detecting a value of a selection signal VCOSEL[m-1:0] by which the desired VCO frequency fVCO is obtained, in discretely adjusting process, increase in proportion to the number of fixed-value capacitors included in the VCO unit 110. Hence, when the VCO unit 110 includes many fixed-value capacitors, long times are necessary to detect the final objective selection signal VCOSEL[m-1:0], so that the demands of “high-speed responsibility” and “wider bandwidth” for the VCO unit and the PLL unit cannot be obtained.
It means that, in order to realize the demand of “wider bandwidth”, it is necessary to increase the number of fixed-value capacitors C0, C1, C2, . . . , Cm-1, shown in FIG. 14. However, the increase of the number of the fixed-value capacitors means the extension of the range of the selection signal VCOSEL[m-1:0] shown in FIG. 16. Assuming that the selection signal VCOSEL[m-1:0] is expressed in binary values, the range of the value of the selection signal becomes 0 to 2m−1. For example, if the number of the fixed-value capacitors is 10, the selection signal VCOSEL[m-1:0] will be expressed in 10 bit-binary values, thus the range of the value of the selection signal becomes 0 to 1023.
As for the PLL frequency synthesizer shown in FIG. 14, discretely adjusting process for the VCO frequency fVCO is controlled by the VCO selector unit 120. In this case, firstly, the convergence test of the VCO frequency fVCO at a certain point with an expected value is operated. When the VCO frequency fVCO at the point does not satisfy the convergence range, a binary test in which the frequency fVCO is higher (or lower) than the expected value is judged is operated. Then, the selection signal VCOSEL [m-1:0] is changed by 1 on the basis of the binary test. Then the convergence test is operated again. These processes are repeated until the frequency fVCO satisfies the convergence range.
In the case where the number of the fixed-value capacitors is 10, and the selection signal VCOSEL[m-1:0] is expressed in 10 bit-binary values, as described above, if the initial value of the selection signal VCOSEL[m-1:0] is “0”, the convergence test is repeated at most 1023 times. Even if the initial value of the selection signal VCOSEL [m-1:0] is set as “511” to decrease the number of convergence tests, the test is repeated at most 512 times.
Therefore, it has been a problem in the conventional PLL frequency synthesizer that the demands of “high-speed responsibility” and “wider bandwidth” are incompatible because the time required for the discretely adjusting process for the VCO frequency fVCO increases in proportion to “wider bandwidth”.
In addition, as for the techniques described in the publications mentioned above, it is difficult to actualize the demands of “high-speed responsibility” and “wider bandwidth” at the same time.